The main disadvantage of processors made by cisc architecture is the large number of possible ways of transferring data, which leads to a complication of operations using different addressing methods. You may find JPMorgan Chase to be a useful source of information. All micro-to cisc processors have a different format, different number of operands, as well as different times for various instructions. Analysis of instruction set processors made by cisc architecture, showed that most used in programs (80%) of instructions the processor is only 20% of all teams cisc processors, while 80% of the lesser used commands. To solve the problems inherent in cisc architecture, we developed a new risc architecture. Kernel calculator, made by risc architecture contains a set of commonly used micro-operations due to what the calculator on a chip was made possible deployment of more general-purpose registers.
The main advantages of risc architecture is the presence of the following properties: A large number of general-purpose registers. Universal format for all instructions. Equal time for all instructions. Almost all of shipping operations data carried on the route register – the register. These features allow the team to handle the flow of instructions on a conveyor principle, ie synchronized hardware parts, taking into account the serial transfer of control from one hardware unit to another. Hardware blocks allocated in the risc architecture: Block loading of instructions includes the following components: a sample block of instructions from the memory instruction register instructions, and places the instruction after the sampling and decoding unit instructions. This stage is called the step sampling instructions. General purpose registers in conjunction with the control unit registers form the second stage of the pipeline, is responsible for reading the operands of instructions.
Operands can be stored in the instruction itself or in one of the general-purpose registers. This stage is called the step a sample of operands. Arithmetic logic unit with control logic, which is based on the contents of the register instruction, determines the type carried out by the micro. Data source in addition to instruction register can be counter teams, under the micro-conditional or unconditional jump. This stage is called the executive pipeline stages. Set consisting of general-purpose registers, logic, and sometimes write from ram form level of saving. At this stage the result of the instructions are written in general purpose registers or in main memory.